Survey of approaches and techniques for security verification of computer systems


This article surveys the landscape of security verification approaches and techniques for computer systems at various levels: from a software-application level all the way to the physical hardware level. Different existing projects are compared, based on the tools used and security aspects being examined. Since many systems require both hardware and software components to work together to provide the system’s promised security protections, it is not sufficient to verify just the software levels or just the hardware levels in a mutually exclusive fashion. This survey especially highlights system levels that are verified by the different existing projects and presents to the readers the state of the art in hardware and software system security verification. Few approaches come close to providing full-system verification, and there is still much room for improvement.

ACM Journal on Emerging Technologies in Computing Systems (JETC)
Ferhat Erata
Ferhat Erata
PhD Candidate at Yale | Applied Scientist Intern at AWS

My research interests include automated reasoning, program analysis, formal verification, security, and property synthesis.